The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a measure to restrain a reverse narrow channel effect from occurring in a transistor having a narrow gate width.
In recent years, for the purpose of reducing the cost of a semiconductor device (LSI), there has been a strong demand for increased density of an SRAM circuit placed in an LSI. In order to increase the density of the SRAM circuit, it is significant to shorten the gate length of a transistor that is an element of the SRAM circuit, but it is still unavoidable to reduce the width of an isolation isolating elements from one another. In order to reduce the isolation width, reduction in the gate width of the transistor has been indispensable.
As the gate width of a transistor is reduced, the reverse narrow channel effect that the threshold voltage drops becomes more significant. When the reverse narrow channel effect takes place, threshold voltages of transistors having different gate widths differ from one another, leading to variations in leakage current and saturation current and reduction in circuit performance (see, for example, Japanese Laid-Open Patent Publication No. 11-233729 (page 2, FIGS. 2 through 5)).
To cope with this, the following method for fabricating a semiconductor device has conventionally been employed as means for avoiding the reverse narrow channel phenomenon.
FIGS. 5A through 5E show known process steps for fabricating a semiconductor device in cross section taken along the gate width direction.
The semiconductor device shown in FIGS. 5A through 5E includes a logic circuit formation region Rlogc and a memory circuit formation region Rmemo. A logic MIS transistor Ltr having a wide gate width of approximately 0.4 μm is formed in the logic circuit formation region Rlogc. A memory cell MIS transistor Mtrs having a narrow gate width of approximately 0.1 μm and a peripheral MIS transistor Mtrl having a wide gate width of approximately 0.4 μm are formed in the memory circuit formation region Rmemo.
First, in a process step shown in FIG. 5A, an underlying oxide film 102 and a nitride film 103 are successively formed on the whole surface of a P-type semiconductor substrate 101, and thereafter a resist mask 104 is formed on the nitride film 103 to cover a region for forming an active region.
Next, in a process step shown in FIG. 5B, dry etching is performed on the nitride film 103 and the underlying oxide film 102 by using the resist film 104 as a mask so that a protective dielectric 103a and an underlying dielectric 102a are formed, and thereafter the resist film 104 is removed.
Next, in a process step shown in FIG. 5C, a known trench isolation formation process step allows the semiconductor substrate 101 to be partly etched away to a predetermined depth by dry etching using the protective dielectric 103a as a mask to form an isolation trench (not shown), and then an oxide film (HDP-NSG film) is deposited on the whole surface of the substrate by a high-density plasma method. Thereafter, parts of the HDP-NSG film located on the protective dielectric 103a are removed using a CMP method, and then the protective dielectric 103a and the underlying dielectric 102a are selectively removed by etching. This allows an isolation 105 to be formed by filling the isolation trench with the HDP-NSG film.
Next, in a process step shown in FIG. 5D, a protective film 106 made of an oxide film is formed on the active region of the semiconductor substrate 101, and then P-type impurities (for example, boron (B+) or boron fluoride (BF2+)) are ion-implanted into the substrate 101 for the purpose of adjusting the threshold voltage of the logic MIS transistor Ltr, thereby forming a first low-concentration impurity implantation region 107 in the logic circuit formation region Rlogc. At this time, a first low-concentration impurity implantation region 107 is formed also in the memory circuit formation region Rmemo.
Next, in a process step shown in FIG. 5E, a resist film 108 is formed on the substrate to cover the logic circuit formation region Rlogc while the memory circuit formation region Rmemo is open. Thereafter, P-type impurities (for example, boron (B+) or boron fluoride (BF2+)) are additionally ion-implanted into the substrate using the resist film 108 as a mask for the purpose of adjusting the threshold voltage of the memory cell MIS transistor Mtrs (i.e., the substrate is subjected to an additional ion implantation for adjusting the threshold voltage), thereby forming a second low-concentration impurity implantation region 109 in the memory circuit formation region Rmemo.
Thereafter, the resist film 108 is removed, and then the protective film 106 is removed. Thereafter, a gate dielectric, a gate electrode, source and drain regions, and the like are formed, whereby a logic MIS transistor having a wide gate width is formed in the logic circuit formation region Rlogc and a memory cell MIS transistor Mtrs having a narrow gate width and a peripheral MIS transistor Mtrl having a wide gate width are formed in the memory circuit formation region Rmemo. Impurities in the first and second low-concentration impurity implantation regions 107 and 109 are diffused using a thermal oxidation process, a Rapid Thermal Annealing (RTA) process for the activation of impurities or like processes, thereby forming first and second impurity diffusion regions.
According to this known method for fabricating a semiconductor device, reduction in the threshold voltage occurring in the transistor region where the gate width is narrow can be adjusted by the additional ion implantation. Thereby, the threshold voltage of the logic MIS transistor Ltr having a wide gate width and the threshold voltage of the memory cell MIS transistor Mtrs having a narrow gate width can be adjusted to become substantially the same.